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1 ltc1096/ltc1096l ltc1098/ltc1098l micropower sampling 8-bit serial i/o a/d converters d u escriptio s f ea t u re n 80 m a maximum supply current n 1na typical supply current in shutdown n 8-pin so plastic package n 5v operation (ltc1096/ltc1098) n 3v operation (ltc1096l/ltc1098l)(2.65v min) n sample-and-hold n 16 m s conversion time n 33khz sample rate n 0.5lsb total unadjusted error over temp n direct 3-wire interface to most mpu serial ports and all mpu parallel i/o ports the ltc ? 1096/ltc1096l/ltc1098/ltc1098l are micropower, 8-bit a/d converters that draw only 80 m a of supply current when converting. they automatically power down to 1na typical supply current whenever they are not performing conversions. they are packaged in 8-pin so packages and have both 3v (l) and 5v versions. these 8-bit, switched-capacitor, successive approximation adcs include sample-and-hold. the ltc1096/ltc1096l have a single differential analog input. the ltc1098/ltc1098l offer a software selectable 2-channel mux. on-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. this, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. these circuits can be used in ratiometric applications or with an external reference. the high impedance analog inputs and the ability to operate with reduced spans (below 1v full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. u s a o pp l ic at i n battery-operated systems n remote data acquisition n battery monitoring n battery gas gauges n temperature measurement n isolated data acquisition , ltc and lt are registered trademarks of linear technology corporation. supply current vs sample rate sample frequency, f smpl (khz) 0.1 1 supply current, i cc ( m a) 10 100 1000 1 10 100 ltc1096/98 ?tpc03 t a = 25? v cc = v ref = 5v 10 m w, s8 package, 8-bit a/d samples at 200hz and runs off a 5v battery 5v 1 m f analog input 0v to 5v range ?n gnd v cc clk d out v ref ltc1096 mpu (e.g., 8051) p1.4 p1.3 p1.2 +in ltc1096/8 ?ta01 cs/ shutdown u a o pp l ic at i ty p i ca l
2 ltc1096/ltc1096l ltc1098/ltc1098l a u g w a w u w a r b s o lu t exi t i s operating temperature ltc1096ac/ltc1096c/ltc1096lc/ ltc1098ac/ltc1098c/LTC1098LC ....... 0 c to 70 c ltc1096ai/ltc1096i/ltc1096li/ ltc1098ai/ltc1098i/ltc1098li ..... C 40 c to 85 c lead temperature (soldering, 10 sec.) ................ 300 c supply voltage (v cc ) to gnd ................................... 12v voltage analog and reference ................ C0.3v to v cc + 0.3v digital inputs ......................................... C0.3v to 12v digital outputs ........................... C0.3v to v cc + 0.3v power dissipation .............................................. 500mw storage temperature range ................. C 65 c to 150 c (notes 3) wu u package / o rder i for atio order part number ltc1098acn8 ltc1098acs8 ltc1098ain8 ltc1098ais8 ltc1098cn8 ltc1098cs8 ltc1098in8 ltc1098is8 LTC1098LCs8 ltc1098lis8 (notes 1 and 2) order part number ltc1096acn8 ltc1096acs8 ltc1096ain8 ltc1096ais8 ltc1096cn8 ltc1096cs8 ltc1096in8 ltc1096is8 ltc1096lcs8 ltc1096lis8 1 2 3 4 8 7 6 5 top view +in in gnd v cc clk d out v ref n8 package 8-lead plastic dip cs/ shutdown s8 package 8-lead plastic soic t jmax = 150 c, q ja = 130 c/w (n8) t jmax = 150 c, q ja = 175 c/w (s8) s8 part marking 1096 1096a 1096l 1096li 1096i 1096ia 1 2 3 4 8 7 6 5 top view ch0 ch1 gnd v cc (v ref) clk d out d in n8 package 8-lead plastic dip cs/ shutdown s8 package 8-lead plastic soic t jmax = 150 c, q ja = 130 c/w (n8) t jmax = 150 c, q ja = 175 c/w (s8) 1098l 1098li 1098 1098a 1098i 1098ia consult factory for military grade parts. reco e ded operati g co ditio s w u w u u u symbol parameter conditions min typ max units v cc supply voltage ltc1096 3.0 9 v ltc1098 3.0 6 v v cc = 5v operation f clk clock frequency v cc = 5v 25 500 khz t cyc total cycle time ltc1096, f clk = 500khz 29 m s ltc1098, f clk = 500khz 29 m s t hdi hold time, d in after clk - v cc = 5v 150 ns t sucs setup time cs before first clk - (see operating sequence) v cc = 5v, ltc1096 500 ns v cc = 5v, ltc1098 500 ns t wakeup wake-up time cs before first clk after first clk - v cc = 5v, ltc1096 10 m s (see figure 1 ltc1096 operating sequence) wake-up time cs before msbf bit clk v cc = 5v, ltc1098 10 m s (see figure 2 ltc1098 operating sequence) t sudi setup time, d in stable before clk - v cc = 5v 400 ns t whclk clk high time v cc = 5v 0.8 m s s8 part marking ltc1096/ltc1098
3 ltc1096/ltc1096l ltc1098/ltc1098l reco e ded operati g co ditio s w u w u u u symbol parameter conditions min typ max units v cc supply voltage 2.65 4.0 v f clk clock frequency v cc = 2.65v 25 250 khz t cyc total cycle time ltc1096l, f clk = 250khz 58 m s ltc1098l, f clk = 250khz 58 m s t hdi hold time, d in after clk - v cc = 2.65v 450 ns t sucs setup time cs before first clk - (see operating sequence) v cc = 2.65v, ltc1096l 1 m s v cc = 2.65v, ltc1098l 1 m s t wakeup wake-up time cs before first clk after first clk - v cc = 2.65v, ltc1096l 10 m s (see figure 1, ltc1096l operating sequence) wake-up time cs before msbf bit clk v cc = 2.65v, ltc1098l 10 m s (see figure 2, ltc1098l operating sequence) t sudi setup time, d in stable before clk - v cc = 2.65v 1 m s t whclk clk high time v cc = 2.65v 1.6 m s t wlclk clk low time v cc = 2.65v 1.6 m s t whcs cs high time between data transfer cycles v cc = 2.65v 2 m s t wlcs cs low time during data transfer ltc1096l, f clk = 250khz 56 m s ltc1098l, f clk = 250khz 56 m s ltc1096/ltc1098 symbol parameter conditions min typ max units t wlclk clk low time v cc = 5v 0.8 m s t whcs cs high time between data transfer cycles v cc = 5v 1 m s t wlcs cs low time during data transfer ltc1096, f clk = 500khz 28 m s ltc1098, f clk = 500khz 28 m s v cc = 3v operation f clk clock frequency v cc = 3v 25 250 khz t cyc total cycle time ltc1096, f clk = 250khz 58 m s ltc1098, f clk = 250khz 58 m s t hdi hold time, d in after clk - v cc = 3v 450 ns t sucs setup time cs before first clk - (see operating sequence) v cc = 3v, ltc1096 1 m s v cc = 3v, ltc1098 1 m s t wakeup wake-up time cs before first clk after first clk - v cc = 3v, ltc1096 10 m s (see figure 1 ltc1096 operating sequence) wake-up time cs before msbf bit clk v cc = 3v, ltc1098 10 m s (see figure 2 ltc1098 operating sequence) t sudi setup time, d in stable before clk - v cc = 3v 1 m s t whclk clk high time v cc = 3v 1.6 m s t wlclk clk low time v cc = 3v 1.6 m s t whcs cs high time between data transfer cycles v cc = 3v 2 m s t wlcs cs low time during data transfer ltc1096, f clk = 250khz 56 m s ltc1098, f clk = 250khz 56 m s ltc1096l/ltc1098l
4 ltc1096/ltc1096l ltc1098/ltc1098l co verter a d ultiplexer characteristics uu w ltc1096/ltc1098 ltc1096a/ltc1098a parameter conditions min typ max min typ max units resolution (no missing code) l 8 8 bits offset error l 0.5 0.5 lsb linearity error (note 4) l 0.5 0.5 lsb full scale error l 0.5 1.0 lsb total unadjusted error (note 5) v ref = 5.000v l 0.5 1.0 lsb analog input range (notes 6, 7) v ref input range (notes 6, 7) 4.5 v cc 6v v 6v < v cc 9v, ltc1096 v analog input leakage current (note 8) l 1.0 1.0 m a C 0.05v to v cc + 0.05v C 0.05v to v cc + 0.05v C 0.05v to 6v ltc1096/ltc1098 v cc = 5v, v ref = 5v, f clk = 500khz, unless otherwise noted. ltc1096/ltc1098 ltc1096a/ltc1098a parameter conditions min typ max min typ max units resolution (no missing code) l 8 8 bits offset error l 0.75 1.0 lsb linearity error (notes 4, 9) l 0.5 1.0 lsb full-scale error l 1.0 1.0 lsb total unadjusted error (notes 5, 9) v ref = 2.500v l 1.0 1.5 lsb analog input range (notes 6, 7) v ref input range (notes 6, 7, 9) 3v v cc 6v v analog input leakage current ( notes 8, 9 ) l 1.0 1.0 m a C 0.05v to v cc + 0.05v C 0.05v to v cc + 0.05v ltc1096/ltc1098 v cc = 3v, v ref = 2.5v, f clk = 250khz, unless otherwise noted. ltc1096l/ltc1098l parameter conditions min typ max units resolution (no missing code) l 8 bits offset error l 1.0 lsb linearity error (note 4) l 1.0 lsb full-scale error l 1.0 lsb total unadjusted error (notes 5) v ref = 2.5v l 1.5 lsb analog input range (notes 6, 7) C 0.05v to v cc + 0.05v v ref input range (note 6) 2.65v v cc 4.0v C 0.05v to v cc + 0.05v v analog input leakage current (note 8) l 1.0 m a ltc1096l/ltc1098l v cc = 2.65v, v ref = 2.5v, f clk = 250khz, unless otherwise noted.
5 ltc1096/ltc1096l ltc1098/ltc1098l digital a n d dc electrical characteristics u symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.0 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 4.75v, i o = 10 m a l 4.5 4.74 v v cc = 4.75v, i o = 360 m a l 2.4 4.72 v v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz hi-z output leakage cs 3 v ih l 3.0 m a i source output source current v out = 0v C 25 ma i sink output sink current v out = v cc 45 ma i ref reference current cs = v cc l 0.001 2.5 m a t cyc 3 200 m s, f clk 50khz l 3.500 7.5 m a t cyc = 29 m s, f clk = 500khz l 35.000 50.0 m a i cc supply current cs = v cc l 0.001 3.0 m a ltc1096, t cyc 3 200 m s, f clk 50khz l 40 80 m a ltc1096, t cyc = 29 m s, f clk = 500khz l 120 180 m a ltc1098, t cyc 3 200 m s, f clk 50khz l 44 88 m a ltc1098, t cyc = 29 m s, f clk = 500khz l 155 230 m a ltc1096/ltc1098 v cc = 5v, v ref = 5v, unless otherwise noted. symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v l 1.9 v v il low level input voltage v cc = 3v l 0.45 v i ih high level input current (note 9) v in = v cc l 2.5 m a i il low level input current (note 9) v in = 0v l C2.5 m a v oh high level output voltage v cc = 3v, i o = 10 m a l 2.3 2.69 v v cc = 3v, i o = 360 m a l 2.1 2.64 v v ol low level output voltage v cc = 3v, i o = 400 m a l 0.3 v i oz hi-z output leakage (note 9) cs 3 v ih l 3.0 m a i source output source current (note 9) v out = 0v C 10 ma i sink output sink current (note 9) v out = v cc 15 ma i ref reference current (note 9) cs = v cc l 0.001 2.5 m a t cyc 3 200 m s, f clk 50khz l 3.500 7.5 m a t cyc = 58 m s, f clk = 250khz l 35.000 50.0 m a i cc supply current (note 9) cs = v cc l 0.001 3.0 m a ltc1096, t cyc 3 200 m s, f clk 50khz l 40 80 m a ltc1096, t cyc = 58 m s, f clk = 250khz l 120 180 m a ltc1098, t cyc 3 200 m s, f clk 50khz l 44 88 m a ltc1098, t cyc = 58 m s, f clk = 250khz l 155 230 m a ltc1096/ltc1098 v cc = 3v, v ref = 2.5v, unless otherwise noted.
6 ltc1096/ltc1096l ltc1098/ltc1098l digital a n d dc electrical characteristics u ltc1096l/ltc1098l v cc = 2.65v, v ref = 2.5v, f clk = 250khz, unless otherwise noted. symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v l 1.9 v v il low level input voltage v cc = 2.65v l 0.45 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 2.65v, i o = 10 m a l 2.3 2.64 v v cc = 2.65v, i o = 360 m a l 2.1 2.50 v v ol low level output voltage v cc = 2.65v, i o = 400 m a l 0.3 v i oz hi-z output leakage cs = high l 3.0 m a i source output source current v out = 0v C 10 ma i sink output sink current v out = v cc 15 ma i ref reference current cs = v cc l 0.001 2.5 m a t cyc 3 200 m s, f clk 50khz l 3.500 7.5 m a t cyc = 58 m s, f clk = 250khz l 35.000 50.0 m a i cc supply current cs = v cc l 0.001 3.0 m a ltc1096l, t cyc 3 200 m s, f clk 50khz l 40 80 m a ltc1096l, t cyc = 58 m s, f clk = 250khz l 120 180 m a ltc1098l, t cyc 3 200 m s, f clk 50khz l 44 88 m a ltc1098l, t cyc = 58 m s, f clk = 250khz l 155 230 m a ac characteristics ltc1096/ltc1098 v cc = 5v, v ref = 5v, f clk = 500khz, unless otherwise noted. symbol parameter conditions min typ max units t smpl analog input sample time see operating sequence 1.5 clk cycles f smpl (max) maximum sampling frequency l 33 khz t conv conversion time see operating sequence 8 clk cycles t ddo delay time, clk to d out data valid see test circuits l 200 450 ns t dis delay time, cs - to d out hi-z see test circuits l 170 450 ns t en delay time, clk to d out enable see test circuits l 60 250 ns t hdo time output data remains valid after clk c load = 100pf 180 ns t f d out fall time see test circuits l 70 250 ns t r d out rise time see test circuits l 25 100 ns c in input capacitance analog inputs on channel 25 pf analog inputs off channel 5 pf digital input 5 pf
7 ltc1096/ltc1096l ltc1098/ltc1098l symbol parameter conditions min typ max units t smpl analog input sample time see operating sequence 1.5 clk cycles f smpl(max) maximum sampling frequency l 16.5 khz t conv conversion time see operating sequence 8 clk cycles t ddo delay time, clk to d out data valid see test circuits (note 9) l 500 1000 ns t dis delay time, cs - to d out hi-z see test circuits (note 9) l 220 800 ns t en delay time, clk to d out enable see test circuits (note 9) l 160 480 ns t hdo time output data remains valid after clk c load = 100pf 400 ns t f d out fall time see test circuits (note 9) l 70 250 ns t r d out rise time see test circuits (note 9) l 50 150 ns c in input capacitance analog inputs on channel 25 pf analog inputs off channel 5 pf digital input 5 pf ltc1096/ltc1098 v cc = 3v, v ref = 2.5v, f clk = 250khz, unless otherwise noted. ltc1096l/ltc1098l v cc = 2.65v, v ref = 2.5v, f clk = 250khz, unless otherwise noted. symbol parameter conditions min typ max units t smpl analog input sample time see operating sequence 1.5 clk cycles f smpl(max) maximum sampling frequency l 16.5 khz t conv conversion time see operating sequence 8 clk cycles t ddo delay time, clk to d out data valid see test circuits l 500 1000 ns t dis delay time, cs - to d out hi-z see test circuits l 220 800 ns t en delay time, clk to d out enable see test circuits l 160 480 ns t hdo time output data remains valid after clk c load = 100pf 400 ns t f d out fall time see test circuits l 70 250 ns t r d out rise time see test circuits l 50 200 ns c in input capacitance analog inputs on channel 25 pf analog inputs off channel 5 pf digital input 5 pf the l denotes specifications which apply over the operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: for the 8-lead pdip, consult the factory. note 4: linearity error is specified between the actual and points of the a/d transfer curve. note 5: total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. note 6: two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below gnd or one diode drop above v cc . this spec allows 50mv forward bias of either diode. this means that as long as the reference or analog input does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v over initial tolerance, temperature variations and loading. for 5.5v < v cc 9v, reference and analog input range cannot exceed 5.55v. if reference and analog input range are greater than 5.55v, the output code will not be guaranteed to be correct. note 7: the supply voltage range for the ltc1096l/ltc1098l is from 2.65v to 4v. the supply voltage range for the ltc1096 is from 3v to 9v, but the supply voltage range for the ltc1098 is only from 3v to 6v. note 8: channel leakage current is measured after the channel selection. note 9: these specifications are either correlated from 5v specifications or guaranteed by design. ac characteristics
8 ltc1096/ltc1096l ltc1098/ltc1098l reference voltage (v) 0 magnitude of offset change (lsb = 1/256 v ref ) 0 0.25 4 ltc1096/98 ?tpc04 0.25 0.50 1 2 3 5 0.50 t a = 25? v cc = 5v f clk = 500khz change in offset vs supply voltage change in linearity vs reference voltage ltc1096 change in gain vs supply voltage supply voltage, v cc (v) 0 magnitude of offset change (lsb) 0.1 0.3 0.5 8 ltc1096/98 ?tpc05 0.1 0.3 0.5 2 4 6 10 0 0.2 0.4 0.2 0.4 19 3 5 7 t a = 25? v ref = 2.5v f clk = 100khz change in offset vs reference voltage ltc1096 supply current vs supply voltage active and shutdown modes supply current vs clock rate for active and shutdown modes supply current vs sample frequency ltc1096 frequency (khz) 1 0 supply current, i cc ( m a) 150 200 250 10 100 1000 ltc1096/98 ?tpc01 100 50 t a = 25 c cs = 0v v cc = 9v v cc = 5v cs = v cc 10 0.002 supply voltage,v cc (v) 0 0 supply current, i cc ( m a) 20 60 80 100 2 4 59 ltc1096/98 ?tpc02 40 13 6 7 8 t a = 25 c v ref = 2.5v ?ctive?mode cs = 0 ?hutdown?mode cs = v cc 0.001 sample frequency, f smpl (khz) 0.1 1 supply current, i cc ( m a) 10 100 1000 1 10 100 ltc1096/98 ?tpc03 t a = 25? v cc = v ref = 5v reference voltage (v) 0 change in linearity (lsb) 0 0.25 4 ltc1096/98 ?tpc06 0.25 o.50 1 2 3 5 0.50 t a = 25? v cc = 5v f clk = 500khz supply voltage, v cc (v) 0 change in linearty (lsb) 0.1 0.3 0.5 8 ltc1096/98 ?tpc07 0.1 0.3 0.5 2 4 6 10 0 0.2 0.4 0.2 0.4 19 3 5 7 t a = 25 c v ref = 2.5v f clk = 100khz change in linearity vs supply voltage supply voltage, v cc (v) 0 change in gain (lsb) 0.1 0.3 0.5 8 ltc1096/98 ?tpc08 0.1 0.3 0.5 2 4 6 10 0 0.2 0.4 0.2 0.4 19 3 5 7 t a = 25 c v ref = 2.5v f clk = 100khz voltage reference (v) 0 change in gain (lsb) 0 0.25 4 ltc1096/98 ?tpc09 0.25 o.50 1 2 3 5 0.50 t a = 25? v cc = 5v f clk = 500khz change in gain vs reference voltage ltc1096 cc hara terist ics uw a t y p i ca lper f o r c e
9 ltc1096/ltc1096l ltc1098/ltc1098l supply voltage, v cc (v) 0 logic thresh0ld (v) 3 4 5 8 ltc1096/98 ?tpc12 2 1 0 2 4 6 10 t a = 25 c digital input logic threshold vs supply voltage maximum clock frequency vs supply voltage maximum clock frequency vs source resistance supply voltage (v) 0 0 maximum clock frequency (mhz) 0.25 0.5 0.75 1.0 1.25 1.5 2468 ltc1096/98 ?tpc11 10 t a = 25 c v ref = 2.5v r source (k w ) 1 0 maximum clock frequency* (mhz) 0.25 0.50 1 10 100 ltc1096/98 ?tpc10 0.75 + input ?input r source v in t a = 25? v cc = v ref = 5v wake-up time vs supply voltage supply voltage, v cc (v) 0 wake-up time ( m s) 3 4 8 ltc1096/98 ?tpc13 2 1 0 2 4 6 10 t a = 25 c v ref = 2.5v r source (k w ) 1 0 minimum wake-up time ( m s) 2.5 5.0 10 10 100 ltc1096/98 ?tpc14 7.5 t a = 25 c v ref = 5v + ? v in r source + minimum wake-up time vs source resistance temperature (?) ?0 leakage current (na) 10 100 1000 100 ltc1096/98 ?tpc15 1 0.1 0.01 ?0 20 60 140 ?0 0 40 80 120 v ref = 5v v cc = 5v on channel off channel input channel leakage current vs temperature minimum clock frequency for 0.1lsb error ? vs temperature enobs vs frequency fft plot frequency (khz) 1 0 enobs 2 4 6 8 10 10 100 ltc1096/98 ?tpc17 9 7 5 3 1 t a = 25 c v cc = v ref = 5v f smpl = 31.25khz temperature ( c) ?0 minimum clock frequency (khz) 120 160 200 100 ltc1096/98 tpc16 60 40 0 ?0 20 60 140 ?0 0 40 80 120 v ref = 5v v cc = 5v 180 140 100 80 20 frequency (khz) 0 100 amplitude (db) ?0 ?0 ?0 ?0 0 ?0 2 4 ltc1096/98 ?tpc18 ?0 ?0 ?0 ?0 6 8 10 12 14 16 t a = 25 c v cc = v ref = 5v f smpl = 31.25khz f in = 5.8khz * maximum clk frequency represents the clock frequency at which a 0.1lsb shift in the error at any code transition from its 0.75mhz value is first detected. ? as the clk frequency is decreased from 500khz, minimum clk frequency ( d error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code transition from its 500khz value is first detected. cc hara terist ics uw a t y p i ca lper f o r c e
10 ltc1096/ltc1096l ltc1098/ltc1098l w i dagra b l o c k pi fu ctio s u uu ltc1096/ltc1096l cs/shdn (pin 1): chip select input. a logic low on this input enables the ltc1096/ltc1096l. a logic high on this input disables the ltc1096/ltc1096l and disconnects the power to the ltc1096/ltc1096l. in + (pin 2): analog input. this input must be free of noise with respect to gnd. in C (pin 3): analog input. this input must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. v ref (pin 5): reference input. the reference input defines the span of the a/d converter and must be kept free of noise with respect to gnd. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer. v cc (pin 8): power supply voltage. this pin provides power to the a/d converter. it must be free of noise and ripple by bypassing directly to the analog ground plane. ltc1098/ltc1098l cs/shdn (pin 1): chip select input. a logic low on this input enables the ltc1098/ltc1098l. a logic high on this input disables the ltc1098/ltc1098l and disconnects the power to the ltc1098/ltc1098l. ch0 (pin 2): analog input. this input must be free of noise with respect to gnd. ch1 (pin 3): analog input. this input must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. d in (pin 5): digital data input. the multiplexer address is shifted into this pin. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer. v cc (v ref )(pin 8): power supply voltage. this pin pro- vides power and defines the span of the a/d converter. it must be free of noise and ripple by bypassing directly to the analog ground plane. + c sample bias and shutdown circuit serial port v cc (v cc /v ref ) cs clk d out in + (ch0) in (ch1) micropower comparator capacitive dac sar v ref gnd pin names in parentheses refer to the ltc1098/ltc1098l (d in ) ltc1096/ltc1096l
11 ltc1096/ltc1096l ltc1098/ltc1098l d out waveform 1 (see note 1) 2.0v t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. ltc1096/98 ?tc06 d out 3k 100pf test point 5v t dis waveform 2, t en t dis waveform 1 ltc1096/98 ?tc05 load circuit for t dis and t en test circuits on and off channel leakage current load circuit for t ddo , t r and t f 5v a a i off i on polarity off channel on channel ltc1096/98 ?tc1 ? ? ? d out 1.4v 3k w 100pf test point ltc1096/98 ?tc02 voltage waveforms for d out delay time, t ddo voltage waveforms for d out rise and fall times, t r , t f clk d out v il t ddo v oh v ol ltc1096/98 ?tc03 d out t r t f ltc1096/98 ?tc04 v oh v ol voltage waveforms for t dis
12 ltc1096/ltc1096l ltc1098/ltc1098l voltage waveforms for t en ltc1096/98 ?tc07 cs t wakeup ltc1096/ltc1096l 1 clk d out t en b7 v ol 12345 ltc1098/ltc1098l d in clk d out start t en b7 ltc1096/98 ?tc08 cs v ol u s a o pp l ic at i wu u i for atio overview the ltc1096/ltc1096l/ltc1098/ltc1098l are 8-bit micropower, switched-capacitor a/d converters. these sampling adcs typically draw 120 m a of supply current when sampling up to 33khz. supply current drops linearly as the sample rate is reduced (see supply current vs sample rate on the first page of this data sheet). the adcs automatically power down when not performing conver- sion, drawing only leakage current. they are packaged in 8-pin so packages. the ltc1096l/ltc1098l operate on a single supply ranging from 2.65v to 4v. the ltc1096 operates on a single supply ranging from 3v to 9v while the ltc1098 operates from 3v to 6v supplies. the ltc1096/ltc1096l/ltc1098/ltc1098l comprise an 8-bit, switched-capacitor adc, a sample-and-hold and a serial port (see block diagram). although they share the same basic design, the ltc1096(l) and ltc1098(l) differ in some respects. the ltc1096(l) has a differential input and has an external reference input pin. it can measure signals floating on a dc common mode voltage and can operate with reduced spans down to 250mv. reducing the span allows it to achieve 1mv resolution. the ltc1098(l) has a 2-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. serial interface the ltc1098(l) communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface while the ltc1096(l) uses a 3-wire interface (see operating sequence in figures 1 and 2). test circuits
13 ltc1096/ltc1096l ltc1098/ltc1098l clk t cyc cs b7* b6 b5 b4 b3 b2 b1 b0 b1 b2 b3 b4 b5 b6 b7 null bit hi-z d out ltc1096/98 f01 power down hi-z t sucs t wakeup t conv clk cs t cyc power down t wakeup b0 b1 b2 b3 b4 b5 b6 b7 hi-z d out t conv hi-z t sucs null bit *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely. (msb) (msb) figure 1. ltc1096(l) operating sequence u s a o pp l ic at i wu u i for atio power down and wake-up time the ltc1096(l)/ltc1098(l) draw power when the cs pin is low and shut themselves down when that pin is high. in order to have a correct conversion result, a 10 m s wake-up time must be provided from cs falling to the first falling clock (clk) after the first rising clk for the ltc1096(l) and from cs falling to the msbf bit clk falling for the ltc1098(l) (see operating sequence). if the ltc1096(l)/ ltc1098(l) are running with clock frequency less than or equal to 100khz, the wake-up time is inherently provided. example two cases are shown at right to illustrate the relationship among wake-up time, setup time and clk frequency for the lt1096(l). in case 1 the clock frequency is 100khz. one clock cycle is 10 m s which can be the wake-up time, while half of that can be the setup time. in case 2 the clock frequency is 50khz, half of the clock cycle plus the setup time (=1 m s) can be the wake-up time. if the clk frequency is higher case 1. timing diagram case 2. timing diagram cs ltc1096/98 ?ai ex. clk null bit b7 t wakeup 10? t su t su t wakeup d out cs clk d out than 100khz, figure 1 shows the relationship between the wake-up time and setup time. the wake-up time is inherently provided for the ltc1098(l) with setup time = 1 m s (see figure 2).
14 ltc1096/ltc1096l ltc1098/ltc1098l data transfer the clk synchronizes the data transfer with each bit being transmitted on the falling clk edge and captured on the rising clk edge in both transmitting and receiving sys- tems. the ltc1098(l) first receives input data and then transmits back the a/d conversion result (half duplex). because of the half duplex operation, d in and d out may be tied together allowing transmission over just three wires: cs, clk and data (d in /d out ). data transfer is initiated by a falling chip select (cs) signal. after cs falls the ltc1098(l) looks for a start bit. after the start bit is received, the 3-bit input word is shifted into the d in input which configures the ltc1098(l) and starts the conversion. after one null bit, the result of the conversion u s a o pp l ic at i wu u i for atio clk cs t cyc power down t sucs t wakeup d in sgl/ diff msbf b0* b1 b2 b3 b4 b5 b6 b7 null bit hi-z d out t conv t smpl hi-z start odd/ sign don't care msb-first data (msbf = 0) msb-first data (msbf = 1) ltc1096/98 f02 clk cs t cyc power down t sucs t wakeup d in sgl/ diff msbf b0 b1 b2 b3 b4 b5 b6 b7 null bit hi-z d out t conv t smpl hi-z start odd/ sign don't care b7* b6 b5 b4 b3 b2 b1 *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely. (msb) (msb) figure 2. ltc1098(l) operating sequence example: differential inputs (ch + , ch C ) d in 1 d in 2 d out 1 d out 2 cs shift mux address in 1 null bit shift a/d conversion result out ltc1096/98 ?ai01 is output on the d out line. at the end of the data exchange cs should be brought high. this resets the ltc1098(l) in preparation for the next data exchange. the ltc1096(l) does not require a configuration input word and has no d in pin. a falling cs initiates data transfer as shown in the ltc1096(l) operating sequence. after cs falls, the first clk pulse enables d out . after one null bit,
15 ltc1096/ltc1096l ltc1098/ltc1098l sgl/ diff odd/ sign msbf start mux address msb-first/ lsb-first ltc1096/8 ?ai02 start bit the first logical one clocked into the d in input after cs goes low is the start bit. the start bit initiates the data transfer. the ltc1098(l) will ignore all leading zeros which precede this logical one. after the start bit is received, the remaining bits of the input word will be clocked in. further inputs on the d in pin are then ignored until the next cs cycle. multiplexer (mux) address the bits of the input word following the start bit assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the followintg tables. in single-ended mode, all input channels are measured with respect to gnd. msb-first/lsb-first (msbf) the output data of the ltc1098(l) is programmed for msb-first or lsb-first sequence using the msbf bit. when the msbf bit is a logical one, data will appear on the d out line in msb-first format. logical zeros will be filled in indefinitely following the last data bit. when the msbf bit is a logical zero, lsb-first data will follow the normal msb-first data on the d out line. (see operating sequence) unipolar transfer curve the ltc1096(l)/ltc1098(l) are permanently config- ured for unipolar only. the input span and code assign- ment for this conversion type are shown in the follow- ing figures for a 5v reference. unipolar transfer curve 0v 1lsb v ref ?lsb v ref ?lsb v ref v in 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ltc1096/8 ?ai04 the a/d conversion result is output on the d out line. bringing cs high resets the ltc1096(l) for the next data exchange. input data word the ltc1096(l) requires no d in word. it is permanently configured to have a single differential input. the conver- sion result, in which output on the d out line is msb-first sequence, followed by lsb sequence providing easy inter- face to msb- or lsb-first serial ports. the ltc1098(l) clocks data into the d in input on the rising edge of the clock. the input data words are defined as follows: u s a o pp l ic at i wu u i for atio ltc1098(l) channel selection mux address sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + 1 + ? + gnd ? ? single-ended mux mode differential mux mode ltc1096/8 ?ai03 operation with d in and d out tied together the ltc1098(l) can be operated with d in and d out tied together. this eliminates one of the lines required to communicate to the microprocessor (mpu). data is trans- mitted in both directions on a single wire. the processor pin connected to this data line should be configurable as either an input or an output. the ltc1098(l) will take control of the data line and drive it low on the 4th falling unipolar output code output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb ? ? ? 1lsb 0v input voltage (v ref = 5.000v) 4.9805v 4.9609v ? ? ? 0.0195v 0v ltc1096/8 ?ai05
16 ltc1096/ltc1096l ltc1098/ltc1098l 1 2 3 4 cs clk data (d in /d out ) start sgl/diff odd/sign msbf b7 b6 msbf bit latched by ltc1098(l) ltc1098(l) controls data line and sends a/d result back to mpu mpu controls data line and sends mux address to ltc1098(l) processor must release data line after 4th rising clk and before the 4th falling clk ltc1098(l) takes control of data line on 4th falling clk ltc1-96/8 ?f03 u s a o pp l ic at i wu u i for atio figure 3. ltc1098(l) operation with d in and d out tied together clk edge after the start bit is received (see figure 3). therefore the processor port line must be switched to an input before this happens, to avoid a conflict. in the typical applications section, there is an example of interfacing the ltc1098(l) with d in and d out tied to- gether to the intel 8051 mpu. achieving micropower performance with typical operating currents of 40 m a and automatic shutdown between conversions, the ltc1096/ltc1098 achieves extremely low power consumption over a wide range of sample rates (see figure 4). in systems that convert continuously, the ltc1096/ltc1098 will draw its normal operating power continuously. figure 5 shows that the typical current varies from 40 m a at clock rates below 50khz to 100 m a at 500khz. several things must be taken into account to achieve such a low power consumption. shutdown figures 1 and 2 show the operating sequence of the ltc1096/ltc1098. the converter draws power when the cs pin is low and powers itself down when that pin is high. if the cs pin is not taken to ground when it is low and not taken to supply voltage when it is high, the input buffers of clock frequency (hz) 20 supply current, i cc ( m a) 60 80 120 140 100 10k 100k 1m ltc1096/98 ?f05 0 1k 100 40 0.002 t a = 25? v cc = 5v active (cs low) shutdown (cs high) active and shutdown modes sample frequency, f smpl (khz) 0.1 1 supply current, i cc ( m a) 10 100 1000 1 10 100 ltc1096/98 ?tpc03 t a = 25? v cc = v ref = 5v figure 4. automatic power shutdown between conversions allows power consumption to drop with sample rate figure 5. after a conversion, when the microprocessor drives cs high, the adc automatically shuts down until the next conversion. the supply current, which is very low during cconversions, drops to zero in shutdown
17 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i wu u i for atio the converter will draw current. this current may be larger than the typical supply current. it is worthwhile to bring the cs pin all the way to ground when it is low and all the way to supply voltage when it is high to obtain the lowest supply current. when the cs pin is high (= supply voltage), the converter is in shutdown mode and draws only leakage current. the status of the d in and clk input have no effect on supply current during this time. there is no need to stop d in and clk with cs = high, except the mpu may benefit. minimize cs low time in systems that have significant time between conver- sions, lowest power drain will occur with the minimum cs low time. bringing cs low, waiting 10 m s for the wake-up time, transferring data as quickly as possible, and then bringing it back high will result in the lowest current drain. this minimizes the amount of time the device draws power. even though the device draws more power at high clock rates, the net power is less because the device is on for a shorter time. d out loading capacitive loading on the digital output can increase power consumption. a 100pf capacitor on the d out pin can more than double the 100 m a supply current drain at a 500khz clock frequency. an extra 100 m a or so of current goes into charging and discharging the load capacitor. the same goes for digital lines driven at a high frequency by any logic. the cxvxf currents must be evaluated and the troublesome ones minimized. lower supply voltage for lower supply voltages, ltc offers the ltc1096l/ ltc1098l. these pin compatible devices offer specified performance to 2.65v min supply. operating on other than 5v supplies the ltc1096 operates from 3v to 9v supplies and the ltc1098 operates from 3v to 6v supplies. to operate the ltc1096/ltc1098 on other than 5v supplies, a few things must be kept in mind. wake-up time a 10 m s wake-up time must be provided for the adcs to convert correctly on a 5v supply. the wake-up time is typically less than 3 m s over the supply voltage range (see typical curve of wake-up time vs supply voltage). with 10 m s wake-up time provided over the supply range, the adcs will have adequate time to wake up and acquire input signals. input logic levels the input logic levels of cs, clk and d in are made to meet ttl on 5v supply. when the supply voltage varies, the input logic levels also change. for the ltc1096/ltc1098 to sample and convert correctly, the digital inputs have to meet logic low and high levels relative to the operating supply voltage (see typical curve of digital input logic threshold vs supply voltage). if achieving micropower consumption is desirable, the digital inputs must go rail- to-rail between supply voltage and ground (see achiev- ing micropower performance section). clock frequency the maximum recommended clock frequency is 500khz for the ltc1096/ltc1098 running off a 5v supply. with the supply voltage changing, the maximum clock fre- quency for the devices also changes (see the typical curve of maximum clock rate vs supply voltage). if the maxi- mum clock frequency is used, care must be taken to ensure that the device converts correctly. mixed supplies it is possible to have a microprocessor running off a 5v supply and communicate with the ltc1096/ltc1098 operating on 3v or 9v supplies. the requirement to achieve this is that the outputs of cs, clk and d in from the mpu have to be able to trip the equivalent inputs of the adcs and the output of d out from the adcs must be able to toggle the equivalent input of the mpu (see typical curve of digital input logic threshold vs supply voltage). with the ltc1096 operating on a 9v supply, the output of d out may go between 0v and 9v. the 9v output may damage the mpu running off a 5v supply. the way to get around this possibility is to have a resistor divider on d out
18 ltc1096/ltc1096l ltc1098/ltc1098l figure 7. ltc1098(l) + and C input settling windows clk d in d out "+" input "? input sample hold "+" input must settle during this time t smpl t conv cs sgl/diff start msbf don't care 1st bit test "? input must settle during this time b7 ltc1096/8 ?f07 u s a o pp l ic at i wu u i for atio (figure 6) and connect the center point to the mpu input. it should be noted that to get full shutdown, the cs input of the ltc1096/ltc1098 must be driven to the v cc voltage. this would require adding a level shift circuit to the cs signal in figure 6. +in ?n gnd v cc clk d out v ref 50k 50k 6v 4.7 m f mpu (e.g. 8051) 5v p1.4 p1.3 p1.2 ltc1096/98 ?f06 differential inputs common mode range 0v to 6v 9v ltc1096 9v optional level shift cs figure 6. interfacing a 9v powered ltc1096 to a 5v system board layout considerations grounding and bypassing the ltc1096(l)/ltc1098(l) should be used with an ana- log ground plane and single point grounding tech niques. the gnd pin should be tied directly to the ground plane. the v cc pin should be bypassed to the ground plane with a 1 m f tantalum with leads as short as possible. if power supply is clean, the ltc1096(l)/ltc1098(l) can also operate with smaller 0.1 m f surface mount or ceramic bypass capacitors. all analog inputs should be referenced directly to the single point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. sample-and-hold both the ltc1096(l) and the ltc1098(l) provide a built- in sample-and-hold (s&h) function to acquire signals. the s&h of the ltc1096(l) acquires input signals from + input relative to C input during the t wakeup time (see figure 1). however, the s&h of the ltc1098(l) can sample input signals in the single-ended mode or in the differential inputs during the t smpl time (see figure 7). single-ended inputs the sample-and-hold of the ltc1098(l) allows conver- sion of rapidly varying signals. the input voltage is sampled during the t smpl time as shown in figure 7. the sampling interval begins as the bit preceding the msbf bit is shifted
19 ltc1096/ltc1096l ltc1098/ltc1098l in and continues until the falling clk edge after the msbf bit is received. on this falling edge, the s&h goes into hold mode and the conversion begins. differential inputs with differential inputs, the adc no longer converts just a single voltage but rather the difference between two volt- ages. in this case, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. however, the volt- age on the selected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be per- formed accurately. the conversion time is 8 clk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input this error would be: v error (max) = v peak ? 2 ? p ? f(C) ? 8/f clk where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f clk is the frequency of the clk. in most cases v error will not be significant. for a 60hz signal on the C input to generate a 1/4lsb error (5mv) with the converter running at clk = 500khz, its peak value would have to be 750mv. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1096(l)/ ltc1098(l )have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem. however, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to ensure that the transients caused by the current spikes settle completely before the conversion begins. + input settling the input capacitor of the ltc1096(l) is switched onto + input during the wake-up time (see figure 1) and samples the input signal within that time. however, the input capacitor of the ltc1098(l) is switched onto + input during the sample phase (t smpl , see figure 7). the sample phase is 1.5 clk cycles before conversion starts. the voltage on the + input must settle completely within t wakeup or t smpl for the ltc1096(l) or the ltc1098(l) respectively. minimizing r source + and c1 will improve the input settling time. if a large + input source resis- tance must be used, the sample time can be increased by using a slower clk frequency. C input settling at the end of the t wakeup or t smpl , the input capacitor switches to the C input and conversion starts (see figures 1 and 7). during the conversion the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the C input voltage settles completely during the first clk cycle of the conversion time and be free of noise. minimizing r source C and c2 will improve settling time. if a large C input source resistance must be used, the time allowed for settling can be extended by using a slower clk frequency. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figure 7). again, the + and C input sampling times can be extended as described above to accommodate slower op amps. most op amps, including the lt1006 and lt1413 single supply op amps, can be made to settle well even with the minimum settling windows of 3 m s (+ input) which occur at the maximum clock rate of 500khz. source resistance the analog inputs of the ltc1096/ltc1098 look like a 25pf capacitor (c in ) in series with a 500 w resistor (r on ) as shown in figure 8. c in gets switched between the selected + and C inputs once during each conversion u s a o pp l ic at i wu u i for atio r on = 500 w c in = 25pf ltc1096 ltc1098 ?? input r source + v in + c1 ? input r source v in ? c2 ltc1096/8 ?f8 figure 8. analog input equivalent circuit
20 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i wu u i for atio tive current spike will be generated on the reference pin by the adc. these current spikes settle quickly and do not cause a problem. using a slower clk will allow more time for the reference to settle. even at the maximum clk rate of 500khz most references and op amps can be made to settle within the 2 m s bit time. cycle. large external source resistors and capacitances will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within the allowed time. rc input filtering it is possible to filter the inputs with an rc network as shown in figure 9. for large values of c f (e.g., 1 m f), the capacitive input switching currents are averaged into a net dc current. therefore, a filter should be chosen with a small resistor and large capacitor to prevent dc drops across the resistor. the magnitude of the dc current is approximately i dc = 25pf(v in /t cyc ) and is roughly pro- portional to v in . when running at the minimum cycle time of 29 m s, the input current equals 4.3 m a at v in = 5v. in this case, a filter resistor of 390 w will cause 0.1lsb of full- scale error. if a larger filter resistor must be used, errors can be eliminated by increasing the cycle time. r filter v in c filter ltc1096/8 ?f9 ltc1098 ? i dc figure 9. rc input filtering input leakage current input leakage currents can also create errors if the source resistance gets too large. for instance, the maximum input leakage specification of 1 m a (at 125 c) flowing through a source resistance of 3.9k will cause a voltage drop of 3.9mv or 0.2lsb. this error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of input channel leakage current vs tem- perature). reference inputs the voltage on the reference input of the ltc1096 defines the voltage span of the a/d converter. the reference input transient capacitive switching currents due to the switched- capacitor conversion technique (see figure 10). during each bit test of the conversion (every clk cycle), a capaci- figure 10. reference input equivalent circuit r on 5pf to 30pf ltc1096 ref + r out v ref every clk cycle 5 4 gnd ltc1096/8 ?f10 reduced reference operation the minimum reference voltage of the ltc1098 is limited to 3v because the v cc supply and reference are internally tied together. however, the ltc1096 can operate with reference voltages below 1v. the effective resolution of the ltc1096 can be increased by reducing the input span of the converter. the ltc1096 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of linearity and full scale error vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following fac- tors must be considered when operating at low v ref values. 1. offset 2. noise 3. conversion speed (clk frequency) offset with reduced v ref the offset of the ltc1096 has a larger effect on the output code when the adc is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to
21 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i wu u i for atio reference voltage for a typical value of v os . for example, a v os of 2mv which is 0.1lsb with a 5v reference becomes 0.5lsb with a 1v reference and 2.5lsbs with a 0.2v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input of the ltc1096. noise with reduced v ref the total input referred noise of the ltc1096 can be reduced to approximately 1mv peak-to-peak using a ground plane, good bypassing, good layout techniques and mini- mizing noise on the reference inputs. this noise is insig- nificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. for operation with a 5v reference, the 1mv noise is only 0.05lsb peak-to-peak. in this case, the ltc1096 noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1v reference, this same 1mv noise is 0.25lsb peak-to- peak. this will reduce the range of input voltages over which a stable output code can be achieved by 1lsb. if the reference is further reduced to 200mv, the 1mv noise becomes equal to 1.25lsbs and a stable code may be difficult to achieve. in this case averaging readings may be necessary. this noise data was taken in a very clean setup. any setup- induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise free setup. conversion speed with reduced v ref with reduced reference voltages the lsb step size is reduced and the ltc1096 internal comparator over- drive is reduced. therefore, it may be necessary to reduce the maximum clk frequency when low values of v ref are used. input divider it is ok to use an input divider on the reference input of the ltc1096 as long as the reference input can be made to settle within the bit time at which the clock is running. when using a larger value resistor divider on the reference input the C input should be matched with an equivalent resistance. bypassing reference input with divider bypassing the reference input with a divider is also pos- sible. however, care must be taken to make sure that the dc voltage on the reference input will not drop too much below the intended reference voltage. ac performance two commonly used figures of merit for specifying the dynamic performance of the adcs in digital signal pro- cessing applications are the signal-to-noise ratio (snr) and the effective number of bits (enobs). signal-to-noise ratio t he signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. this includes distortion as well as noise products and for this reason it is sometimes referred to as signal-to-noise + distortion [s/(n + d)]. the output is band limited to frequencies from dc to one half the sampling frequency. figure 11 shows spectral content from dc to 15.625khz which is 1/2 the 31.25khz sam- pling rate. frequency (khz) 0 amplitude (db) ?0 ?0 ?0 16 ltc1096/8 ?f11 ?0 ?0 120 4 8 12 100 0 ?0 ?0 ?0 ?0 110 2 6 10 14 f sample = 31.25khz f in = 11.8khz figure 11. this clean fft of an 11.8khz input shows remarkable performance for an adc that draws only 100 m a when sampling at the 31.25khz rate
22 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i wu u i for atio effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an a/d and is directly related to the s/(n + d) by the equation: enob = [s/(n + d) C1.76]/6.02 where s/(n + d) is expressed in db. at the maximum sampling rate of 33khz the ltc1096 maintains 7.5 enobs or better to 40khz. above 40khz the enobs gradually decline, as shown in figure 12, due to increasing second harmonic distortion. the noise floor remains approxi- mately 70db. figure 12. dynamic accuracy is maintained up to an input frequency of 40khz input frequency (khz) 0 effective number of bits (enobs) 3 4 5 ltc1096/8 ?f12 2 1 0 20 40 6 7 8 f sample = 31.25khz u s a o pp l ic at i ty p i ca l microprocessor interfaces the ltc1096(l)/ltc1098(l) can interface directly (with- out external hardware to most popular microprocessor (mpu) synchronous serial formats (see table 1). if an mpu without a dedicated serial port is used, then three or four of the mpus parallel port lines can be programmed to form the serial link to the ltc1096(l)/ltc1098(l). included here is one serial interface example and one example showing a parallel port programmed to form the serial interface. motorola spi (mc68hc05c4,cm68hc11) the mc68hc05c4 has been chosen as an example of an mpu with a dedicated serial port. this mpu transfer data msb-first and in 8-bit increments. with two 8-bit transfers, the a/d result is read into the mpu. the first 8-bit transfer sends the d in word to the ltc1098(l) and clocks into the processor. the second 8-bit trans- fer clocks the a/d conversion result, b7 through b0, into the mpu. anding the first mup received byte with 00hex clears the first byte. notice how the position of the start bit in the first mpu transmit word is used to position the a/d result right-justified in two memory locations. table 1. microprocessor with hardware serial interfaces compatible with the ltc1096(l)/ltc1098(l) * requires external hardware microwire and microwire/plus are trademarks of national semiconductor corp. part number type of interface motorola mc6805s2,s3 spi mc68hc11 spi mc68hc05 spi rca cdp68hc05 spi hitachi hd6305 sci synchronous hd63705 sci synchronous hd6301 sci synchronous hd63701 sci synchronous hd6303 sci synchronous hd64180 csi/o national semiconductor cop400 family microwire tm cop800 family microwire/plus tm ns8050u microwire/plus hpc16000 family microwir/plus texas instruments tms7002 serial port tms7042 serial port tms70c02 serial port tms70c42 serial port tms32011* serial port tms32020 serial port
23 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i ty p i ca l mpu transmit word cs clk d out mpu received word d in 00 01 odd/ sign msbf x sgl/ diff xxxxxxxx start bit byte 1 byte 2 (dummy) x = don't care start sgl/ diff don't care b7 b6 b5 b4 b3 b2 b1 b0 odd/ sign msbf ?? ?? ???0 b7 b6 b5 b4 b3 b2 b1 b0 2nd transfer 1st transfer ltc1096/8 ?ta03 data exchange between ltc1098(l) and mc68hc05c4 hardware and software interface to motorola mc68hc05c4 ltc1096/8 ?ta04 clk d in cs analog inputs c0 sck d out miso mosi mc68hc05c4 ltc1098 location a + 1 lsb location a byte 2 byte 1 ltc1096/8 ?ta05 b7 b6 b5 b4 b3 b2 b1 b0 00 00 0000 d out from ltc1098(l) stored in mc68hc05c4 label mnemonic comments start bclrn bit 0 port c goes low (cs goes low) lda load ltc1098(l) d in word into acc. sta load ltc1098(l) d in word into spi from acc. transfer begins. tst test status of spif bpl loop to previous instruction if not done with transfer lda load contents of spi data register into acc. (d out msbs) sta start next spi cycle and clear the first d out word sta store in memory location a (msbs) tst test status of spif bpl loop to previous instruction if not done with transfer bsetn set b0 of port c (cs goes high) lda load contents of spi data register into acc. (d out lsbs) sta store in memory location a + 1 (lsbs)
24 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i ty p i ca l interfacing to the parallel port of the intel 8051 family the intel 8051 has been chosen to demonstrate the interface between the ltc1098(l) and parallel port micro- processors. normally the cs, clk and d in signals would be generated on three port lines and the d out signal read on a fourth port line. this works very well. however, we will demonstrate here an interface with the d in and d out of the ltc1098(l) tied together as described in the serial interface section. this saves one wire. the 8051 first sends the start bit and mux address to the ltc1098(l) over the data line connected to p1.2. then p1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 8-bit a/d result over the same data line. cs clk d out d in ltc1098(l) analog inputs p1.4 p1.3 p1.2 8051 mux address a/d result ltc1096/8 ?ta06 1 cs clk data (d in /d out ) start odd/ sign msbf b7 msbf bit latched by ltc1098(l) ltc1098(l) sends a/d result back to 8051 p1.2 8051 p1.2 outputs data to ltc1098(l) 8051 p1.2 reconfigured as an input after the 4th rising clk and before the 4th falling clk ltc1098(l) takes control of data line on 4th falling clk 234 sgl/ diff b6 b5 b4 b3 b2 b1 b0 ltc1096/8 ?ta08 label mnemonic operand comments mov a, #ffh d in word for ltc1098(l) setb p1.4 make sure cs is high clr p1.4 cs goes low mov r4, #04 load counter loop 1 rlc a rotate d in bit into carry clr p1.3 clk goes low mov p1.2, c output d in bit to ltc1098(l) setb p1.3 clk goes high djnz r4, loop 1 next bit mov p1, #04 bit 2 becomes an input clr p1.3 clk goes low mov r4, #09 load counter loop mov c, p1.2 read data bit into carry rlc a rotate data bit into acc. setb p1.3 clk goes high clr p1.3 clk goes low djnz r4, loop next bit mov r2, a store msbs in r2 setb p1.4 cs goes high d out from ltc1098(l) stored in 8051 ram r2 ltc1096/8 ?ta07 msb lsb b7 b6 b5 b4 b3 b2 b1 b0
25 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i ty p i ca l a quick look circuit for the ltc1096 users can get a quick look at the function and timing of the lt1096 by using the following simple circuit (figure 13). v ref is tied to v cc . v in is applied to the +in input and the C in input is tied to the ground. cs is driven at 1/16 the clock rate by the 74c161 and d out outputs the data. the output data from the d out pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of cs (figure 14). note the lsb data is partially clocked out before cs goes high. clr clk a b c d p gnd v cc rc qa qb qc qd t load 74c161 v in to oscilloscope clock in 150khz max ltc1096/8 ?f13 v cc clk d out v ref ltc1096 cs ch0 ch1 gnd 4.7 m f 5v 5v + msb (b7) null bit lsb (b0) lsb data (b1) cs clk d out vertical: 5v/div horizontal: 10 m s/div ltc1096 +in in v ref cs clk d out v cc gnd to m p 63.4k 0.01 m f 182k 0.01 m f lt1004-1.2 0.1 m f 3v 75k 678 w 13.5k lm134 ltc1096/8 ?f15 figure 15. the ltc1096s high impedance input connects directly to this temperature sensor, eliminating signal conditioning circuitry in this 0 c to 70 c thermometer figure 14. scope trace the ltc1096 quick look circuit showing a/d output 10101010 (aa hex ) figure 13. quick look circuit for the ltc1096 figure 15 shows a temperature measurement system. the ltc1096 is connected directly to the low cost silicon temperature sensor. the voltage applied to the v ref pin adjusts the full scale of the a/d to the output range of the sensor. the zero point of the converter is matched to the zero output voltage of the sensor by the voltage on the ltc1096s negative input.
26 ltc1096/ltc1096l ltc1098/ltc1098l u s a o pp l ic at i ty p i ca l remote or isolated systems figure 16 shows a floating system that sends data to a grounded host system. the floating circuitry is isolated by two optoisolators and powered by a simple capacitor diode charge pump. the system has very low power requirements because the ltc1096 shuts down between conversions and the optoisolators draw power only when data is being transferred. the system consumes only 50 m a at a sample rate of 10hz (1ms on-time and 99ms off- time). this is easily within the current supplied by the charge pump running at 5mhz. if a truly isolated system is required, the systems low power simplifies generating an isolated supply or powering the system from a battery. figure 16. power for this floating a/d system is provided by a simple capacitor diode charge pump. the two optoisolators draw no current between samples, turning on only to send the clock and receive data ltc1096 +in in d out cs clk v cc gnd v ref 75k lt1004-2.5 1k 20k 0.1 m f 1n5817 0.022 m f 47 m f 1n5817 1n5817 0.001 m f 2kv 5mhz 100k 300 w 10k 500k analog input floating system clk data 100k ltc1096/8 ?f16 2n3904 +
27 ltc1096/ltc1096l ltc1098/ltc1098l information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u dimensions in inches (millimeters), unless otherwise noted. n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 0695 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.015 (0.380) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) so8 0695 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
28 ltc1096/ltc1096l ltc1098/ltc1098l ? linear technology corporation 1994 10968fb lt/tp 0397 5k rev b ? printed in usa u a o pp l ic at i ty p i ca l linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com related parts part number description comments ltc1196/ltc1198 8-pin so, 1msps, 8-bit adcs low power, small size, low cost ltc1286/ltc1298 8-pin so, 5v micropower, 12-bit adcs 1- or 2-channel, auto shutdown ltc1285/ltc1298 8-pin so, 3v micropower, 12-bit adcs 1- or 2-channel, auto shutdown ltc1400 5v high speed,serial 12-bit adc 400ksps, complete with v ref , clk, sample-and-hold ltc1594/ltc1598 4- and 8-channel, 5v micropower, 12-bit adcs low power, small size, low cost ltc1594l/ltc1598l 4- and 8-channel, 3v micropower, 12-bit adcs low power, small size, low cost a/d conversion for 3v systems the ltc1096/ltc1098 are ideal for 3v systems. figure 17 shows a 3v to 6v battery current monitor that draws only 70 m a from the battery it monitors. the battery current is sensed with the 0.02 w resistor and amplified by the lt1178. the ltc1096 digitizes the amplifier output and sends it to the microprocessor in serial format. the lt1004 provides the full-scale reference for the adc. the other half of the ltc1178 is used to provide low battery detection. the circuits 70 m a supply current is dominated by the op amps and the reference. the circuit can be located near the battery and data transmitted serially to the microprocessor. figure 17. this 0a to 2a battery current monitor draws only 70 m a from a 3v battery + 750k 0.1 m f 0.02 w for 2a full scale 0.2 w for 0.2a full scale 24.9k l o a d 1/2 lt1178 ltc1096 cs gnd v cc clk d out v ref lt1004-1.2 73.2k 470k 20m 470k lo battery 0.1 m f + 3v to 6v to m p + 1/2 lt1178 ltc1096/8 ?f17

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